Meta Unveils MTIA 300 Training Accelerator with Integrated Networking
The company places six 800 Gbps RDMA interfaces on each of two chiplets inside the package, delivering 1.2 TB/s of I/O bandwidth for recommendation model training.
Menlo Park2 min read
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Meta on August 24 introduced MTIA 300, the first training accelerator in its new family of internally developed chips optimised for recommendation and ranking models.
The defining feature is the integration of networking directly into the processor package. Two chiplets each contain six custom 800 Gbps RDMA interfaces, providing a combined 1.2 TB/s of input/output bandwidth without crossing a PCIe bus.
Meta says the design treats communication as a first-class element rather than an afterthought handled by general-purpose cores. The company co-designed the hardware with its HCCL communication library to match the traffic patterns of large recommendation models.
In production tests on a 150-billion-parameter recommendation model running across 40 accelerators, MTIA 300 reduced total communication time by a factor of 3.9 compared with an equivalent GPU cluster. Within a single rack the system achieved up to 940 GB/s of communication bandwidth.
The chip is aimed at Meta's own ranking and recommendation workloads, which dominate the company's AI infrastructure spending. By moving network interfaces onto the package, Meta seeks to reduce latency and free host CPU resources that would otherwise manage data movement.
MTIA 300 is the first in a planned family. Future variants are expected to cover both training and inference for the same class of models. Meta has not released pricing or external availability details, indicating the silicon is intended primarily for internal data centres.
The announcement comes as major technology firms accelerate custom silicon programmes to escape the cost and supply constraints of merchant GPUs. Meta's approach focuses on the specific communication patterns of recommendation systems rather than general large-language-model training.
Engineers at the company published a detailed technical description on the Engineering at Meta blog, including diagrams of the chiplet layout and performance comparisons. Independent verification of the claimed speed-ups is not yet available.
The move also reduces Meta's exposure to export controls and allocation decisions by external chip suppliers. By controlling both the accelerator and the communication fabric, the company gains tighter control over performance and cost for its largest AI workloads.
